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[VHDL-FPGA-Verilog] riscpu

Description: 一个32位微处理器的verilog实现源代脉,采用5级流水线和cache技术.-a 32 Microprocessor verilog achieve pulse generation sources, used five lines and cache technology.
Platform: | Size: 152576 | Author: 大为 | Hits:

[VHDL-FPGA-Verilog] simple_cpu

Description: 初学cpu结构的很好的verilog代码的示例，适合初学者-novice cpu structure of the good verilog code examples for beginners
Platform: | Size: 79872 | Author: mapleni | Hits:

[ARM-PowerPC-ColdFire-MIPS] leg_source

Description: verilog hdl编写,六段流水线CPU.程序完整，功能强惊。分为多模块编写-verilog hdl prepared replace pipelined CPU. The integrity of the process, strong function scared. Divided into multiple modules prepared
Platform: | Size: 656384 | Author: lumingzhi | Hits:

[VHDL-FPGA-Verilog] Verilog11

Description: 这个是用可编程器件进行仿真CPU的程序，大家一起分享拉-this device is programmable CPU simulation procedures to share with everyone Rafah
Platform: | Size: 18432 | Author: 982134 | Hits:

[SCM] verilog_cpu

Description: 一个小单片机的verilog源代码, 包含说明文档-a small SCM verilog source code contains documentation
Platform: | Size: 16384 | Author: Charles Wen | Hits:

[Software Engineering] VerilogHDL_p2s_s2p

Description: 在微型计算机系统中, CPU与外部的基本通信方式有两种,一种是并行通信即数据的各位同 时传送,其优点是传输速度较快,但数据有多少位就需要多少条传送线 而串行通信中数据一位一位顺序传 送,能节省传送线. 用Verilog HDL语言实现了串并、并串通信接口之间的转换-In the micro-computer system, CPU and the outside of the basic means of communication there are two types of parallel data communication that is transmitted at the same time you have the advantage of faster transfer speeds, but data on the number of those who need the number of transmission line and string A line of data communications, a sequence of transmission, transmission lines can be saved. using Verilog HDL language and realize the string, and string conversions between the communication interface
Platform: | Size: 372736 | Author: 陈东 | Hits:

[ARM-PowerPC-ColdFire-MIPS] RISC_Core.ZIP

Description: 这是一篇关于8位RISC CPU设计的文章，其中包含了用Verilog语言编写的CPU内核程序-This is an 8-bit RISC CPU on the design of the article, which includes using the Verilog language CPU core procedures
Platform: | Size: 340992 | Author: jinzhoulang | Hits:

[VHDL-FPGA-Verilog] elock.verilog.pdf

Description: 一种基于Verilog的电子密码锁的论文介绍。有部分程序代码。-Verilog-based electronic locks thesis introduction. Some program code.
Platform: | Size: 294912 | Author: 李里 | Hits:

[VHDL-FPGA-Verilog] simu_NIOS

Description: 和NIOS功能一样的CPU，可以在FPGA上运行,Verilog源代码-NIOS function and the same CPU, the FPGA can run, Verilog source code
Platform: | Size: 53248 | Author: zx | Hits:

[Windows Develop] simplecpu

Description: 一个16位简单CPU的Verilog源代码。-A CPU of 16 simple Verilog source code.
Platform: | Size: 79872 | Author: qiuyuwu | Hits:

[Windows Develop] CPU_interface_verilog_code

Description: 包括一个基本的CPU接口的verilog程序及激励程序。-Including a basic Verilog CPU interface procedures and incentive program.
Platform: | Size: 1024 | Author: 幻婳 | Hits:

[Other] RiscCpu

Description: Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware description language, and design methods. The procedure adopted ModelSim simulation. BUAA
Platform: | Size: 9216 | Author: sss | Hits:

[OS program] 16cpu

Description: 实现16位的cpu设计 内容使用verilog hdl实现，具体的实现步骤方法，都已经写到文档里面去了！-To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
Platform: | Size: 440320 | Author: gimel_sh | Hits:

[Other Embeded program] 1-in_clk

Description: Verilog HDL编写的4条指令CPU-Verilog HDL prepared four instructions CPU
Platform: | Size: 93184 | Author: liming | Hits:

[VHDL-FPGA-Verilog] TINY3

Description: verilog 编写的tiny cpu 代码，可实现简单的指令和计算-Verilog prepared tiny cpu code, can be simple instructions and the calculation
Platform: | Size: 1660928 | Author: songbo | Hits:

[OS program] 8086IP

Description: 开源CPU软核8086的源码,波兰版Verilog源码-8086 soft-core CPU revenue source, the Polish version of Verilog source code
Platform: | Size: 71680 | Author: 林丹 | Hits:

[VHDL-FPGA-Verilog] RISC8.ZIP

Description: verilog RISC8 cpu CORE 8位RISC CPU 内核源码（VERILOG 版）-verilogRISC8 cpu CORE8-bit RISC CPU core source (VERILOG version)
Platform: | Size: 80896 | Author: likui | Hits:

[VHDL-FPGA-Verilog] mipsCPU

Description: MIPS CPU tested in Icarus Verilog
Platform: | Size: 20480 | Author: imromeo | Hits:

[Windows Develop] RISC_8

Description: 经过验证的8位RISC-CPU源代码，verilog代码，附：汇编测试源代码，而且测试通过。-Verified 8 RISC-CPU source code, verilog code, attached: the compilation of the test source code, and test.
Platform: | Size: 173056 | Author: WangYong | Hits:

[VHDL-FPGA-Verilog] soc-gr0040-010309

Description: xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
Platform: | Size: 406528 | Author: urga turg | Hits:
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